The escalating requirements for density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require planarized layers with minimal spacing between conductive wiring lines.
A traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal-patterning technique. One such traditional technique is illustrated in part in FIGS. 1(a)-1(b), wherein insulative layer 12, such as an oxide layer, is formed on semiconductor substrate 11, such as monocrystalline silicon, with conductive contacts/vias 13 formed in insulative layer 12. A metal layer 14, such as aluminum or tungsten, is deposited on insulating layer 12 and a photoresist pattern 15 formed on metal layer 14 corresponding to the wiring pattern. After etching, a dielectric layer 16 is applied to the resulting wiring pattern 14. The interconnection structure comprises conductive contacts/vias 13 and conductive wiring 14.
In employing such a traditional method, it is extremely difficult to form a planarized layer after filling in the spaces between the conductive wiring 14, as by chemical-mechanical polishing (CMP) planarization techniques. In addition, such a traditional technique often results in the formation of voids 17 as seen in FIG. 1(b) in the spacing between interconnection wirings 14. Additional difficulties include trapping of impurities or volatile materials in the interwiring spaces which may damage the device. Moreover, the traditional etch back approach leads to defects which, even if cosmetic, impose a competitive disadvantage in the commercial environment.
Additional disadvantages of traditional etch back methods include poor metal step coverage, residual metal shorts leading to inconsistent manufacturability, low yields, uncertain reliability and poor ultra large scale integration extendability. Significantly, traditional etch back methods were unable to yield sufficiently planarized layers having interwiring spaces of less than 3.5 microns.
A prior attempt to address the disadvantages attendant upon traditional etch back methods for providing interconnection structures comprises a single damascene wiring technique. Damascene, an art which has been employed for centuries for the fabrication of jewelry, has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled in with a metal. Thus, damascene differs from the traditional etch back methods of providing an interconnection structure by providing a trench which is filled in with metal followed by planarization; whereas, the traditional etch back technique involves building up a metal wiring layer and filling in the interwiring spaces with a dielectric material.
A prior art single damascene technique is illustrated in FIGS. 2(a)-2(e) wherein insulative layer 22 is deposited on semiconductor substrate 21. A photoresist pattern 23 is formed on insulative layer 22 and openings formed in insulative layer 22 by reactive ion etching (RIE). Subsequently, a metal 24, such as tungsten, is deposited within the openings and on insulative layer 22, as by chemical vapor deposition as shown in FIG. 2(d). Alternatively, hot aluminum 25 can be formed in the openings and on insulative layer 22 as shown in FIG. 2(e). Thus, the prior art single damascene technique results in a single conductive opening, e.g., a conductive via. Upon planarization and repetition of the foregoing steps, as by depositing a second insulative layer 33, metal 35 and planarization, an interconnection structure is obtained as shown in FIG. 3. The first layer comprises conductive vias 34 through first insulative layer 32 on semiconductor substrate 31. The conductive wiring 35 in second insulative layer 33 electrically connected to conductive vias 34 at 36.
The single damascene technique offers the advantage of improved planarization; however, it is time consuming in requiring numerous processing steps. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarized layers containing an interwiring spacing less than 0.35 .mu. cannot be obtained.
An improvement in the single damascene process, called dual damascene, has recently been developed by IBM. See, for example, Joshi, "A New Damascene Structure for Submicrometer Interconnect Wiring," IEEE Electron Letters, vol. 14, No. 3, March 1993, pages 129-132; and Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152. The use of a damascene technique wherein the dielectric is planarized by chemical-mechanical polish is discussed in Kenny et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 14 and 15.
U.S. Pat. No. 5,262,354 discloses a three-step method of forming electrically conductive vias and lines involving a damascene technique to create lines on a substrate. In addition, this patent discloses the advantages of chemical-mechanical polishing with an aluminum slurry in dilute nitric acid to planarize a dielectric surface. U.S. Pat. No. 5,093,279 discloses a laser ablation damascene process for planarizing metal/polymer structures in the fabrication of both interlevel via metallization and circuitization layers in integrated circuit interconnects.
The dual damascene technique involves the simultaneous formation of a conductive via and conductive wiring, thereby requiring fewer manipulative steps than the single damascene technique and eliminating the interface between the conductive via and conductive wiring which is necessarily formed by the single damascene technique. The dual damascene technique is illustrated in FIGS. 4(a)-4(c), wherein insulative layer 42 is deposited on semiconductor substrate 41 and then patterned by conventional photolithographic techniques to form a first opening 43 which is about the size of the ultimate via. Subsequently, as shown in FIG. 4(b), photoresist layer 44 is deposited and patterned to form a second opening 45 about the size of the ultimate trench. Anisotropic reactive ion etching (RIE) is then conducted which, in effect, duplicates the first and second openings in insulative layer 42, thereby forming a via and trench. Subsequently, a conductive material such as aluminum, tungsten, copper or alloys thereof, with or without an adhesion/barrier layer, e.g., titanium nitride or a titanium-tungsten alloy, under the conductive material, is provided to form conductive via 46 and conductive wiring 47 as shown in FIG. 4(c). This process is repeated to form a plurality of layers such as second conductive via 48 and second conductive interconnect wiring 49 also shown in FIG. 4(c). The resulting structure is characterized by an interface between the separately formed conductive patterns, i.e., between the first conductive wiring and second conductive via; however, no interface is formed between the conductive via and conductive wiring of each separately formed pattern.
Although the dual damascene technique offers advantages vis-a-vis the traditional etch back technique and the single damascene technique, we have found that it also suffers from several disadvantages. We have found that it is extremely difficult to control the profile of the vias and trenches employing the dual damascene technique and, hence, difficult to control the depth and resistivity of the conductive wiring. Moreover, satisfactory planarized layers having an interwiring spacing of less than 0.35 micron cannot be attained with the above-described dual damascene technique.